1. Field
The present invention relates to integrated circuits and, more particularly, to output driver circuits with auto-equalization based on drive strength calibration.
2. Background
Operating an integrated circuit with precise electric characteristics has become increasingly important. For example, interfaces to memories have increased in speed and require precise driver circuits.
When chip-to-chip interface speeds exceed channel (e.g., the link between a processor or system on a chip (SoC) and memory) bandwidths, it becomes necessary to equalize the transmitted signal. Equalization can take on many forms, but generally it either emphasizes high frequency components or de-emphasizes low frequency components in the signal. The equalization can include, for example, adjusting slew rates of transitions on the transmitted signal and/or adding pre-emphasis by increasing the signal drive at the start of transitions on the output signal.
Various DRAM interface standards include procedures to calibrate the off-chip drive strength and/or the on-die termination resistance. An example procedure includes calibrating, using a voltage-divider technique, either the pull-up or pull-down drive strength relative to a precision resistance mounted on a system board. Then the remaining pull-down or pull-up drive strength is calibrated relative to the calibrated pull-up or pull-down drive strength using a voltage-divider technique.
This calibration is often applied to just one leg of a multi-leg driver, with the additional legs then using the same calibration setting during subsequent operation. For example, traditionally, double data rate (DDR) synchronous dynamic random access memory (SDRAM) interfaces have calibrated a unit pull-up leg to an impedance of 240Ω (ohms) by placing a unit pull-up leg in series with a precision, off-chip, 240Ω resistor and adjusting the strength of the unit pull-up leg so that the voltage between the pull-up leg and the resistor is close to VDDQ/2 (one-half the relevant supply voltage). This type of calibration can provide accurate output impedance but does not provide equalization.
In traditional memory interface standards, equalization is not defined, and no means is built into the specification to calibrate equalization. Thus, if equalization is used, it is typically set based on lab measurements, and the degree of equalization then remains fixed for a particular product design. Thus, integrated circuits fabricated with slow process conditions and integrated circuits fabricated with fast process conditions operate with the same equalization settings. This can result in performance degradation; for example, integrated circuits fabricated with slow process conditions may not amplify high-frequency components sufficiently and integrated circuits fabricated with fast process conditions may have excess high-frequency amplification resulting in excess noise. However, the best performing equalization settings will vary with the specific process conditions used to fabricate a particular product as well as with other conditions that affect performance, for example, temperature and supply voltage.
Accordingly, systems and methods are needed to automatically set the degree of equalization without user input, based on the information made available through the calibration procedures provided by the standards.